80C32 is a high-performance CMOS version of the 8032 NMOS single-chip 8-bit µC. The fully static design of the 80C52/80C32 allows reducing system power consumption by bringing the clock frequency down to any value, even … Read more
RAM
The P80C51 is a high-performance static 80C51 design fabricated with high-density CMOS technology with the operation from 2.7V to 5.5V. The P80C51 contains a 4k × 8 ROM, a 128 × 8 RAM, 32 I/O … Read more
P80C51 CPU with 128×8 RAM 4kBytes ROM and I/O – Datasheet
80C52 is a high-performance CMOS ROM, OTP, EPROM, and ROMless version of the 80C51 CMOS single-chip 8-bit microcontroller. The 80C52 retains all features of the TEMIC 80C51 with extended ROM/EPROM capacity (8Kbytes), 256 bytes of … Read more
P80C52 CPU with 256×8 RAM 8kBytes ROM and I/O – Datasheet
The 80C31 contains a 4k × 8 ROM, a 128 × 8 RAM, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O … Read more
P80C31 CPU with 128×8 RAM and I/O (ROMless) – Datasheet
The 87C51 is a single-chip control-oriented microcontroller. The 87C51BHP is identical to the 87C51BH. When ordering the 87C51BHP, customers must submit the 64-byte encryption table together with the ROM code. Lock bit 1 will be … Read more
87C51 CPU with EPROM and RAM – Datasheet
The 8032 CPU with 256×8 RAM is optimized for control applications. Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The instruction … Read more
8032 CPU with 256×8 RAM – Datasheet
80C32 CPU with 256×8 RAM is a high-performance CMOS version of the 8032 NMOS single-chip 8-bit µC. The fully static design of the 80C32 allows reducing system power consumption by bringing the clock frequency down … Read more
80C32 CPU with 256×8 RAM – Datasheet
The 80C51 is a single-chip control-oriented microcontroller that is fabricated on Intel’s reliable CHMOS III-E technology. Being a member of the 8051 controller family, the 80C51 uses the same powerful instruction set, has the same … Read more
80C51 CPU with 128×8 RAM – Datasheet
80C52 CPU with 256×8 RAM is a high-performance CMOS ROM, OTP, EPROM, and ROM are fewer versions of the 80C51 CMOS single-chip 8-bit microcontroller. The TS80C52 retains all features of the TEMIC 80C51 with extended … Read more
80C52 CPU with 256×8 RAM – Datasheet
The CY7C130 is a high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130 can be utilized as either a standalone 8-bit dual-port … Read more
CY7C130 1Kx8 30ns CMOS RAM – Datasheet
6116 Pinout 6116 Pin Configuration Pin No Pin Name Description 1 A7 Address Pin 7 2 A6 Address Pin 6 3 A5 Address Pin 5 4 A4 Address Pin 4 5 A3 Address Pin 3 … Read more
6116 2Kx8 150ns CMOS RAM – Datasheet
The 8031 CPU with 128×8 RAM and I/O controller is optimized for control applications. Byte-processing and numerical operations on small data structures are facilitated by a variety of fast addressing modes for accessing the internal. … Read more
8031 CPU with 128×8 RAM and I/O – Datasheet
The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), an active … Read more
CY7C185 8Kx8 15ns CMOS RAM – Datasheet
The 23K640 is a 64 Kbit Serial SRAM device. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data … Read more
23K640 64k SPI Bus Serial SRAM – Datasheet
6264 Pinout 6264 Pin Configuration Pin No Pin Name Description 1 NC No Connection 2 A4 Address Pin 4 3 A5 Address Pin 5 4 A6 Address Pin 6 5 A7 Address Pin 7 6 … Read more
6264 8Kx8 120ns CMOS RAM – Datasheet
The CY7C128A is a high-performance CMOS static RAM organized as 2048 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), and active LOW output-enable (OE), and three-state drivers. … Read more