CY7C185 8Kx8 15ns CMOS RAM

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The CY7C185 is a high-performance CMOS static RAM organized as 8192 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), an active LOW output-enable (OE), and three-state drivers. This device has an automatic power-down feature (CE1 or CE2), reducing the power consumption by 70% when deselected. The CY7C185 is in a standard 300-mil-wide DIP and SOJ package.

An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE1 and WE inputs are both LOW and CE2 is HIGH, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A12). Reading the device is accomplished by selecting the device and enabling the outputs, CE1 and OE active LOW, CE2 active HIGH, while WE remain inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.

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CY7C185 Pinout

CY7C185 Pin Configuration

Pin No	Pin Name	Description
1	NC	No Connection
2	A4	Address Pin 4
3	A5	Address Pin 5
4	A6	Address Pin 6
5	A7	Address Pin 7
6	A8	Address Pin 8
7	A9	Address Pin 9
8	A10	Address Pin 10
9	A11	Address Pin 11
10	A12	Address Pin 12
11	I/O 0	Data Inputs/Outputs 0
12	I/O 1	Data Inputs/Outputs 1
13	I/O 2	Data Inputs/Outputs 2
14	GND	Ground Pin
15	I/O 3	Data Inputs/Outputs 3
16	I/O 4	Data Inputs/Outputs 4
17	I/O 5	Data Inputs/Outputs 5
18	I/O 6	Data Inputs/Outputs 6
19	I/O 7	Data Inputs/Outputs 7
20	CE’ 1	Chip Enable Pin 1
21	A0	Address Pin 0
22	OE’	Output Enable Pin
23	A1	Address Pin 1
24	A2	Address Pin 2
25	A3	Address Pin 3
26	CE’ 2	Chip Enable Pin 2
27	WE’	Write Enable Pin
28	VCC	Power Supply Pin