CY7C130 1Kx8 30ns CMOS RAM

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The CY7C130 is a high-speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE), write enable (R/W), and output-enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed in a unique location (3FF for the left port and 3FE for the right port).

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CY7C130 Pinout

CY7C130 Pin Configuration

Pin No	Pin Name	Description
16-23	I/O OL – I/O 7L	Data Inputs/Outputs Pins
25-32	1/O 0R-I/O 7R	Address Inputs/Outputs
33-42	A9R-A0R	Address RESET Pins
6-15	A0L-A9L	Address Latch Pins
1	CE’ L	Chip Latch Enable Pin
2	R/WL	Read Write Latch Pin
3	BUSY’ L	Busy Latch Pin
5	OE’ L	Output Enable Pin
24	GND	Ground Pin
48	VCC	Power Supply
43	OE’ R	Output Enable Reset Pin
44	INT’ R	Interrupt Reset Pin
45	BUSY’R	Busy Reset Pin
46	R/WR’	Read/Write Pin
47	CE’ R	Chip Enable Reset Pin
18	VCC	Power Supply Pin

CY7C130 Key Feature

True Dual-Ported memory cells which allow simultaneous reads of the same memory location
1K x 8 organization
0.65-micron CMOS for optimum speed/power
High-speed access: 15 ns
Low operating power: ICC = 90 mA (max.)
Fully asynchronous operation
Automatic power-down

You can download this datasheet for CY7C130 1Kx8 30ns CMOS RAM – Datasheet from the link given below:

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